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| FDZ202P January 2002 FDZ202P P-Channel 2.5V Specified PowerTrench(R) BGA MOSFET General Description Combining Fairchild's advanced 2.5V specified PowerTrench process with state of the art BGA packaging, the FDZ202P minimizes both PCB space and RDS(ON). This BGA MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, high current handling capability, ultralow profile packaging, low gate charge, and low RDS(ON). Features * -5.5 A, -20 V. RDS(ON) = 45 m @ V GS = -4.5 V RDS(ON) = 75 m @ V GS = -2.5 V * Occupies only 5 mm2 of PCB area: only 55% of the area of SSOT-6 * Ultra-thin package: less than 0.70 mm height when mounted to PCB * Outstanding thermal transfer characteristics: 4 times better than SSOT-6 * Ultra-low Qg x RDS(ON) figure-of-merit * High power and current handling capability Applications * Battery management * Load switch * Battery protection D S G P1 in D S S D D S S D P1 in S F202 G D Bottom Top TA=25oC unless otherwise noted D Absolute Maximum Ratings Symbol V DSS V GSS ID PD TJ , TSTG Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous (Note 1a) - Pulsed Power Dissipation (Steady State) (Note 1a) Operating and Storage Junction Temperature Range Ratings -20 12 -5.5 -20 2 -55 to +150 Units V V A W C Thermal Characteristics RJA RJB RJ C Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) (Note 1) 64 8 0.7 C/W C/W C/W Package Marking and Ordering Information Device Marking 202P Device FDZ202P Reel Size 7'' Tape width 8mm Quantity 3000 units (c)2002 Fairc hild Semiconductor Corporation FDZ202P Rev. C(W) FDZ202P Electrical Characteristics Symbol BV DSS BVDSS TJ IDSS IGSSF IGSSR V GS(th) VGS(th) TJ RDS(on) TA = 25C unless otherwise noted Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, Forward Gate-Body Leakage, Reverse (Note 2) Test Conditions V GS = 0 V, ID = -250 A ID = -250 A, Referenced to 25C V DS = -16 V, V GS = 0 V V GS = -12 V, V DS = 0 V V GS = 12 V, V DS = 0 V V DS = V GS , ID = -250 A ID = -250 A, Referenced to 25C V GS = -4.5 V, ID = -5.5 A V GS = -2.5 V, ID = -4.0 A V GS = -4.5 V, ID = -5.5, TJ =125C V GS = -4.5 V, V DS = -5.0 V V DS = -5 V, ID = -5.5 A Min -20 Typ Max Units V mV/C -1 -100 100 A nA nA V mV/C m Off Characteristics -17 On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) -0.6 -0.9 3 37 57 50 -1.5 45 75 65 ID(on) gFS Ciss Coss Crss -20 15 884 258 103 A S pF pF pF Dynamic Characteristics V DS = -10 V, f = 1.0 MHz V GS = 0 V, Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd IS V SD trr Qrr Notes: 1. Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = -6 V, V GS = -4.5 V, ID = -1 A, RGEN = 6 12 9 36 24 22 18 58 38 13 ns ns ns ns nC nC nC V DS = -10 V, V GS = -4.5 V ID = -5.5 A, 9 2 3 Drain-Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward V GS = 0 V, IS = -1.7 A Voltage Diode Reverse Recovery Time IF = -5.5 A, diF/dt = 100 A/s Diode Reverse Recovery Charge (Note 2) -0.76 25 26 -1.7 -1.2 A V nS nC RJA is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to the circuit board side of the solder ball, RJB, is defined for reference. For RJC, the thermal reference point for the case is defined as the top surface of the copper chip carrier. RJC and RJB are guaranteed by design while RJA is determined by the user's board design. a) 64C/W when mounted on a 1in2 pad of 2 oz copper, 1.5" x 1.5" x 0.062" thick PCB b) 128C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0% FDZ202P Rev C(W) FDZ202P Dimensional Outline and Pad Layout 2.15 1.85 INDEX SLOT C L O 0.40 1 A SYMM C L 2 3 D G S D 0.65 D S S D D S 1.95 B Date/vendor Code F202 SYMM C L 2.70 2.30 C S 0.65 C L D D 1.30 TOP VIEW RECOMMENDED LAND PATTERN 0.76 SOLDER BALL, O 0.30 0.25 C L D SOLDER BALL O 0.30 C 1.95 GATE C L B FRONT VIEW INDEX SLOT (HIDDEN) 0.65 A 1 2 3 0.51 0.65 1.30 BOTTOM VIEW SEATING PLANE SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A) ALL DIMENSIONS ARE IN MILLIMETERS. B) NO JEDEC REGISTRATION REFERENCE AS OF JULY 1999. FDZ202P Rev C(W) FDZ202P Typical Characteristics 20 R DS(ON) NORMALIZED , DRAIN-SOURCE ON-RESISTANCE VGS = -4.5V -3.5V -ID , DRAIN CURRENT (A) 15 -3.0V -2.5V 2 1.8 V GS = -2.5V 1.6 1.4 1.2 1 0.8 0 1 2 3 4 0 5 10 -ID , DRAIN CURRENT (A) 15 20 10 -2.0V 5 -3.0V -3.5V -4.0V -4.5V 0 -V DS, DRAIN-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.18 1.6 RDS(ON) NORMALIZED , DRAIN-SOURCE ON-RESISTANCE RDS(ON) ON-RESISTANCE (OHM) , ID = -5.5A V GS = -4.5V 1.4 ID = -2.8 A 0.14 1.2 0.1 TA = 125 oC 1 0.8 0.06 TA = 25o C 0.02 0.6 -50 -25 0 25 50 75 100 o 125 150 1.5 2 2.5 3 3.5 4 4.5 5 TJ , JUNCTION TEMPERATURE ( C) -V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. 15 V DS = -5V -I D, DRAIN CURRENT (A) -IS, REVERSE DRAIN CURRENT (A) T A = -55oC 25o C 125oC 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 V GS = 0V 10 1 0.1 -55o C TA = 125o C 25o C 5 0.01 0.001 0.0001 0 0.5 1 1.5 2 2.5 3 -V GS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 -V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDZ202P Rev C(W) FDZ202P Typical Characteristics 5 -V GS, GATE-SOURCE VOLTAGE (V) ID = -5.5A 4 CAPACITANCE (pF) -15V 3 V DS = -5V -10V 1600 f = 1MHz V GS = 0 V 1200 C ISS 800 COSS 400 CRSS 2 1 0 0 2 4 6 8 10 12 Qg, GATE CHARGE (nC) 0 0 5 10 15 20 -V DS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 100 R DS(ON) LIMIT ID, DRAIN CURRENT (A) 10 100ms 1 DC V GS = -4.5V SINGLE PULSE RJA = 128o C/W TA = 25o C 0.01 0.1 1 10 100 V DS, DRAIN-SOURCE VOLTAGE (V) 1s 10ms 1ms Figure 8. Capacitance Characteristics. 50 P(pk), PEAK TRANSIENT POWER (W) SINGLE PULSE RJ A = 128C/W TA = 25C 40 30 0.1 20 10 Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 R J A(t) = r(t) + R J A RJ A = 128 C/W P(pk) t1 t2 TJ - TA = P * R J A(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDZ202P Rev C(W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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